The present invention is directed to supply voltage fluctuation (droop and overshoot) detection. More particularly, the present invention is directed to a method and apparatus for detecting on-die voltage fluctuations.
On-die voltage fluctuation (such as voltage droop and/or voltage overshoot) of a power supply is directly related to the performance of a silicon die. As such, Vcc droop measurements may be an integral part of power delivery validation and speed path debug for an entire network from the Vcc regulator on a motherboard to local circuit supplies internal to the die. Low frequency Vcc fluctuations May be monitored by scope measurement on debug pins. That is, a predetermined number of debug pins may be reserved for monitoring Vcc fluctuations on the die. However, one problem is the limited number of debug pins. Another problem is package attenuation, which makes it difficult to observe medium to high frequency droops on the die. High frequency droop measurements across the die may be performed using pico-probing techniques to avoid package attenuation. However, this may require a special pico-probing station, a high bandwidth oscilloscope, successful establishing contact to metal layers on a silicon die, and a lot of effort. An upper limit on the number of post-silicon edits per die may be quickly reached because of the imperfect success rate. The amount and type of data collection may be limited, and thus may not be incorporated into a high volume manufacturing flow.
On-die circuit techniques may have one or more of the following problems. First, the on-die circuit techniques may not be as immune to the surrounding noise. That is, the techniques may require DC-like environments in order to operate correctly. Second, the techniques may be very limited in signal frequency, amplitude or resolution that can be detected. Third, the techniques may require the detected signals to be periodic. Fourth, the modules may not be compact enough or have special analog reference requirements that make them unsuitable for distributed placement on integrated circuits. Fourth, the techniques may need special test equipment setup due to analog inputs/outputs or post-processing requirements.